The present invention relates to semiconductor fabrication, and in particular to forming silicide contacts on a semiconductor device.
The semiconductor industry is continually striving to improve the performance of metal-oxide-semiconductor (MOS) devices. The ability to create devices with sub-micron features has allowed significant performance increases, due to a resulting decrease in the resistances and parasitic capacitances that adversely affect performance. The attainment of sub-micron features has been accomplished via advances in several semiconductor fabrication disciplines. For example, the development of more sophisticated exposure cameras in photolithography, as well as the use of more sensitive photoresist materials, have allowed sub-micron features, in photoresist layers, to be routinely achieved. Additionally, the development of more advanced dry etching tools and processes have allowed the sub-micron images in photoresist layers to be successfully transferred to underlying materials used in MOS structures.
In addition to the contributions supplied by these advances in MOS processing disciplines, performance improvements have also been obtained through use of a salicide process (Self-ALIgned-siliCIDE). Salicide technology comprises forming silicide layers on the source/drain regions and/or on the gate electrode in a self-aligned manner. Salicide technology is improving the performance characteristics of semiconductor devices, and is becoming an essential component of semiconductor device fabrication. As gate electrode lengths are scaled down, the source/drain junctions and polycrystalline line width must also be scaled down. However, scaling down the source/drain junctions and polycrystalline line width increases parasitic resistance in the source/drain diffusion layers and gate electrode diffusion layer, and also increases the sheet and contact resistance of the gate electrode and source/drain regions. Salicide technology reduces parasitic, sheet, and contact resistance in the source/drain diffusion layers and the gate electrode diffusion layer that results from this scaling down of the source/drain junctions and polycrystalline line width.
Silicides are typically formed by reacting a metal with crystallized silicon (Si) within a specified temperature range for a specific period of time. Silicide layers may be self-aligned by different techniques. For example, selectively depositing the metal on the top of the gate electrode and on the source/drain regions of a semiconductor device prior to an annealing process causes only the Si of the source/drain regions and the top of the gate electrode to form silicide upon annealing. Alternatively, sidewall spacers, on the sides of the gate electrode, constructed of a material that does not react with the metal layer, allow a blanket layer of metal to be deposited over a semiconductor device while restricting silicide formation to the exposed source/drain regions and the top of the gate electrode during an annealing process. During the annealing process, the semiconductor device is heated to a reaction temperature, and held at the reaction temperature for a period of time, causing the metal layer to react with the crystallized Si that the metal contacts, thus forming a silicide layer interfacing with the remaining crystallized Si substrate of the source/drain regions and/or the gate electrode. Multiple annealing steps may be employed. Various metals react with Si to form a silicide, however, titaniumn (Ti) and cobalt (Co) are currently the most common metals used to create silicides when manufacturing semiconductor devices utilizing salicide technology. Recently, attention has turned towards using nickel to form NiSi utilizing salicide technology. Using NiSi is advantageous over using TiSi2 and CoSi2 because many limitations associated with TiSi2 and CoSi2 are avoided. When forming NiSi, a low resistivity phase is the first phase to form, and does so at a relatively low temperature. Additionally, nickel (Ni), like Co, diffuses through the film into Si, unlike Ti where the Si diffuses into the metal layer. Diffusion of Ni, and Co, through the film into Si prevents bridging between the silicide layer on the gate electrode and the silicide layer over the source/drain regions. The reaction that forms NiSi requires less Si than when TiSi2 and CoSi2 are formed. Nickel silicide exhibits almost no linewidth dependence of sheet resistance. Nickel silicide is normally annealed in a one step process, versus a process requiring an anneal, an etch, and a second anneal, as is normal for TiSi2 and CoSi2. Nickel silicide also exhibits low film stress, i.e., causes less wafer distortion.
As shown in FIG. 1, a typical semiconductor device, a metal oxide semiconductor field effect transistor (MOSFET), includes a polysilicon gate 100 and an insulating gate oxide layer 110 formed over silicon substrate 120. Deep source/drain regions 140 (sometimes referred to as heavily doped source and drain regions) and source/drain extension regions 150 (sometimes referred to as lightly doped source and drain regions or LDDs) are formed in substrate 120, such as by ion implantation. Typically, once the source/drain extension regions 150 are formed, oxide spacers are formed abutting the gate 100 to protect the source/drain extension regions from further doping while additional ion implantation is performed to form the deep source/drain regions 140. The source/drain extension 150 and deep source/drain 140 are annealed (heated) following ion implantation to obtain the desired material characteristics and to activate the dopants. Generally, doped regions are regions containing a higher concentration of p-type or n-type dopants than the substrate. Also, silicide regions 170 and 160 are typically formed on, over, or within the polysilicon gate 100 and the source/drain regions 140, respectively.
Source/drain extension regions 150 generally have a lower concentration of dopants compared to deep source/drain regions 140, although extension regions 150 are increasingly being endowed with dopant concentrations approaching that of the deep source/drain regions 140. Source/drain extension regions 150 possess a thickness T1 smaller than a corresponding thickness T2 of deep source/drain regions 140. The shallow source/drain extension regions 150 are important, for example, in reducing hot carrier injection (HCI) which often occurs in scaled down (e.g., sub-micron) devices and in reducing short channel effects. For adequate suppression of short channel effects (SCE), the depth of the source drain extension regions should be less than about 700 xc3x85 and preferably less than about 500 xc3x85 and still more preferably less than 300 xc3x85.
A conventional process for forming the MOSFET shown in FIG. 1 is illustrated in FIGS. 2A-2G. Such a process begins with a substrate 200 upon which is deposited or grown an oxide or other insulating layer. A polysilicon layer or layer of other conducting material is formed over the oxide layer followed by patterning and etching to form gate oxide 205 and polysilicon gate 210, as shown in FIG. 2A. Source/drain extension regions 220 are then formed as shown in FIG. 2B, generally by ion implantation with boron, arsenic, or phosphorous ions at energy levels in the range of 1-100 keV. Some processes perform an anneal step following this step to activate doped extension regions 220. Following formation of source/drain extension regions 220, spacers 230 are formed abutting the gate 210 to protect the underlying source/drain extension regions from subsequent implantation used to form the deep source/drain regions 240. The spacers are typically formed by depositing an oxide layer over the entire wafer, including the substrate and gate, by chemical vapor deposition (CVD) or other well-known method followed by anisotropic etching of the oxide to form the spacers 230, as shown in FIG. 2C.
Once spacers 230 are in place, heavily doped source and drain regions (deep source/drain regions) 240 are formed, usually by ion implantation at an energy in the range of 20-120 keV, as shown in FIG. 2D. FIG. 2E shows an anneal (heating) step, wherein the curved lines represent heating of the structure. Annealing reforms the substrate lattice structure and electrically activates the doped regions 220 and 240. Annealing typically is done at temperatures above 900xc2x0 C. and is often performed at temperatures above 1000xc2x0 C. This annealing is rapidly performed, typically lasting for only about 1-60 seconds depending on the particular temperatures used and objects to be achieved, as known to those skilled in the art.
In FIG. 2F, a metal layer 250 is deposited over the source/drain regions 240, the gate structure 210, and sidewall spacers 230. The metal layer 250 can be deposited by a PVD method such as sputtering or evaporation, or a CVD method; and is deposited to a thickness of about 100 xc3x85 to about 500 xc3x85. The deposited metal layer 250 is subsequently annealed in a rapid thermal anneal step to form metal silicide contacts 260 and 270, as shown in FIG. 2G. Nickel silicide, for example, is formed by annealing for about 15 to 120 seconds at between 350xc2x0 C. to 700xc2x0 C.
The thickness of the silicide 260 on the polysilicon gate 210 affects the gate""s resistance and, therefore, the device""s speed. Typically, device performance improves as the gate silicide 260 is made thicker. However, accompanying a thicker gate silicide layer 260 is thicker silicide formation on the source/drain regions 240, which can lead to detrimental effects on a device""s performance. In addition to the silicide layer 270 that forms on the source/drain regions 240, some silicide forms within the source/drain regions 240 and in the source/drain extensions 220. The presence of silicide in the source/drain regions 240 and the extension regions 220 can contribute to unwanted short channel effects, such as junction leakage. More silicide is likely to be formed in the source/drain regions 240 and the extension regions 220 as the thickness of the desirable silicide layer 270 is increased. The device""s performance is also affected by the thickness of the source/drain regions 240 and extension regions 220. When the thicknesses of these regions 220 and 240 are reduced to improve a device""s performance, the amount of excess silicide formation in these regions 220 needed to adversely affect the device (by creating junction leakage) is also reduced.
Accordingly, there exists a need for salicide technology that enables a relatively thick silicide layer to be formed on a polysilicon gate while controlling the thickness of the silicide layer on the source/drain regions and the source/drain extension regions.
These and other needs are met by embodiments of the present invention, which provide a method for forming silicide contacts with two separate metal deposition steps and accompanying silicide formation steps. According to this method, a metal silicide layer is formed over particular regions of a substrate and then selectively removed from some of those regions. A second metal silicide layer is subsequently formed over the particular regions of the substrate and used as metal silicide contacts for the device.
One aspect of the present invention relates to a semiconductor device that includes a substrate with a polysilicon gate and source/drain regions formed on top. A silicide contact is included on the polysilicon gate that is about 5 to 8 times thicker than the silicide contacts on the source/drain regions.
Another aspect of the present invention relates to a method of manufacturing silicide contacts on a semiconductor device that includes forming a gate on a semiconductor substrate, forming at least one source/drain extension region on the substrate, annealing a first deposited metal layer to form metal silicide, removing the metal silicide over the source/drain extension regions while removing only a portion of the silicide over the polysilicon gate, and annealing a second deposited metal layer to form silicide contacts on both the polysilicon gate and the source/drain extension regions.
One further aspect of the present invention relates to a method for forming silicide contacts on a polysilicon gate and source/drain regions that includes the steps of forming silicide on the gate and source/drain regions by annealing a first metal layer, removing a portion of the silicide on the gate and removing substantially all the silicide on the source/drain regions, and then forming the silicide contacts on the gate and source/drain regions by annealing a second metal layer.
Additional advantages and other features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those having ordinary skill in the art upon examination of the following, or may be learned by practice of the invention. The advantages of the present invention may be realized and attained as particularly pointed out in the appended claims The term semiconductor devices, as used herein, is not limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.